The present invention relates generally to a semiconductor device, and more particularly, to a stack package.
In the semiconductor industry, packaging technology for integrated circuits is continuously being developed to satisfy the demands of miniaturization and mounting reliability. For example, the demand for miniaturization has expedited the development of techniques for a package having a size approaching to that of a chip, and the demand for mounting reliability has highlighted the importance of packaging techniques for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
As miniaturization and high performance are demanded in electric and electronic products, new techniques for providing a semiconductor module of high capacity should be developed. One method for providing a semiconductor module of high capacity includes the high integration of a memory chip. The high integration of a memory chip can be accomplished by integrating an increased number of cells in the limited space of the semiconductor chip.
However, the high integration of a memory chip requires high precision techniques, such as a fine line width, and a lengthy development period. Under these situations, a stacking technique has been suggested as another method for providing a semiconductor module of high capacity.
The stacking techniques can generally be divided into methods of embedding two stacked chips in one package and methods of stacking two separate packages which are independently packaged. However, the method of stacking two separate packages cannot accommodate the trend toward miniaturization of electric and electronic products, since each of the separate packages contributes to an increased height and size.
Therefore, a stack package or a multi-chip package realized by embedding at least two semiconductor chips in one package has certain advantages over independently packaged chips.
When manufacturing a stack package, in the case of stacking semiconductor chips of a double bonding pad type, a vertical stacking procedure, in which semiconductor chips are stacked vertically, is mainly adopted. In the case of stacking semiconductor chips of a single bonding pad type, a step-like stacking procedure, in which semiconductor chips are stacked in such a way as to expose the bonding pads thereof, is mainly adopted.
In the conventional art, wires are used to electrically connect the respective stacked semiconductor chips to a substrate. In order to accommodate these wires, the transverse and longitudinal sizes of the finished package must be increased a relatively large degree, whereby difficulties exist in realizing a light, thin, compact and miniaturized structure of the package.
Also, the wire bonding length of upwardly positioned semiconductor chips increases as an increased number of semiconductor chips are stacked, and therefore substantial differences exist in the path lengths of electrical signals for a downwardly positioned semiconductor chip and an upwardly positioned semiconductor chip. Therefore, the electrical signals of the different semiconductor chips of a package are likely to be mismatched.
Moreover, when the stack package is manufactured through the step-like stacking procedure, in addition to the problems caused due to the presence of the wires, a problem is caused in that the transverse size of the package significantly increases as the number of stacked semiconductor chips increases.